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Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the commentary, i.e.:
· a one clock cycle fetch
· a one clock cycle decode
· a two clock cycle execute
and an 80 instruction sequence:
· no pipelining would require _____ clock cycles:
· a scalar pipeline would require _____ clock cycles:
· a superscalar pipeline with two parallel units would require ______ clock cycles:
2. Show the layout of the specified cache for a CPU that can address 1G x 32 of memory. Give the layout of the bits per cache location and the total number of locations.
a) The cache holds 64K x 32 of data and has the fully associative strategy
3. Create a page translation table that meets the requirements of the virtual memory system shown below. Assume page (and frame) sizes of 20 with pages 0 through 4 in logical memory and frames 0 through 7 in physical memory.
4. A computer system using the Relatively Simple CPU has 16K of memory, a segmented Memory Management Unit, and the following segment table (with all numbers in hexadecimal):
5. List the hierarchy of memories with the fastest access time at the top.
6. Match the descriptions below with the most appropriate memory management scheme (A through E). Answers may be used once, more than once, or not at all.
A. Fixed-partition multiprogramming
B. Single task system
C. Variable-partition multiprogramming
D. Virtual memory system with paging
E. Virtual memory system with segmentation
7. Put an “X” next to any of the following that are RISC CPU characteristics that differentiate RISC from CISC
_____________ a) has a limited and simple instruction set
_____________ b) used in IBM 360 processors
_____________ c) uses pipelining
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